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high speed, correlated double sampler with integrated timing driver ad9940 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005 analog devices, inc. all rights reserved. features 56 msps correlated double sampler (cds) with 6 db gain on-chip horizontal and rg timing driver single-supply operation (2.7 v min ) precision timing ? core with 0.37 ns resolution at 56 msps low power cmos: 105 mw at 2.7 v (115 mw at 3.0 v) 48-lead lqfp and 48-lead lfcsp packages applications professional hdtv camcorders professional/high end digital cameras broadcast cameras industrial high speed cameras high speed data-acquisition systems general description the ad9940 is a high speed, correlated double sampler for high speed digital imaging applications. integrated with a programmable timing driver using the precision timing core, the ad9940 features a 56 mhz cds amplifier with 6 db of fixed gain, an internal voltage reference supply, and timing control for all the high speed clocks necessary for ccd imaging systems. the precision timing core allows adjustment of high speed clocks with a resolution of 0.37 ns. output buffers are also included, providing drive strength for pcb traces and direct connection to an image signal processor such as the ad9941. the ad9940 is ideal for applications that need to place the cds and vga/adc circuits on separate pc boards. the fully differential outputs of the ad9940 provide good signal integ- rity when interfaced with the differential input ad9941. the ad9940 operates from a single 2.7 v power supply, typically dissipates 105 mw (excluding the h/rg drive current), and is packaged in 48-lead lqfp and 48-lead lfcsp packages. functional block diagram . diffn ccdin reft refb internal registers sync generator sdisck sl ad9940 precision timing generator v ref internal clocks horizontal drivers hl h1 to h4 hd shp rst 05261-001 4 rg diffp buf cds shd cli figure 1.
ad9940 rev. 0 | page 2 of 20 table of contents specifications..................................................................................... 3 analog specifications................................................................... 4 digital specifications ................................................................... 5 timing specifications (slave timing mode) ............................ 5 absolute maximum ratings............................................................ 6 thermal characteristics .............................................................. 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 data bit descriptions ....................................................................... 9 serial interface timing .................................................................. 12 system overview ............................................................................ 13 analog front end operation.................................................... 13 precision timing, high speed timing generation ................... 14 timing resolution...................................................................... 14 high speed clock programmability........................................ 14 h-driver and rg outputs ........................................................ 16 hblk sequences ........................................................................ 17 application information................................................................ 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history 7/05revision 0: initial version
ad9940 rev. 0 | page 3 of 20 specifications table 1. parameter min typ max unit temperature range operating ?25 +85 c storage ?65 +150 c maximum clock rate 56 mhz power supply voltage avdd, tcvdd (afe, timing core) 2.7 3.0 3.6 v ovdd (analog buffer) 2.7 3.0 3.6 v dvdd (digital) 2.7 3.0 3.6 v hvdd (h1 to h4 drivers) 2.7 3.0 3.6 v rgvdd (rg driver) 2.7 3.0 3.6 v power dissipation 1 56 mhz, afe supplies = 2.7 v, hvdd = rgvdd = 3.2 v, 70 pf, h1 to h4 loading 265 mw 56 mhz, afe supplies = 3.0 v, hvdd = rgvdd = 3.2 v, 70 pf, h1 to h4 loading 275 mw 56 mhz, afe supplies = 2.7 v, no h or rg drivers 105 mw 56 mhz, afe supplies = 3.0 v, no h or rg drivers 115 mw standby mode 2 mw 1 the total power dissipated by the hvdd supply ca n be approximated using the following equation: total hvdd power = ( c load hvdd pixel frequency ) hvdd reducing the h-loading and/or using a lower hvdd supply reduces the power dissipation.
ad9940 rev. 0 | page 4 of 20 analog specifications f cli = 56 mhz, avdd = ovdd = dvdd = tcvdd = 3.0 v, ?25c to +85c, unless otherwise noted. table 2. parameter min typ max unit notes cds gain 5.0 5.5 6.0 db allowable ccd reset transient 1 500 mv maximum input range before saturation 1 1 v p-p maximum ccd black pixel amplitude 1 50 mv peak nonlinearity, 500 mv input signal 0.2 % fs power supply rejection (psr) 36 db me asured with step change on supply analog outputs 2 typical diffp output signal range 1.2 2.2 v 1.2 v corresponds to black level typical diffn output signal range 1.2 2.2 v 2.2 v corresponds to black level typical common mode level 1.7 v midscale voltage where diffp = diffn maximum differential output voltage swing 2 v defined as diffp ? diffn output voltage compliance 1.0 2.4 v limitation of output swing into external load maximum load capacitance 24 pf value for each output (ad9941 c in is < 24 pf) minimum load resistance (if required) 5,000 only use resistive loading if required by the differential receiver. proper dc biasing should be used to be compatible with levels in figure 3 1 input signal characteristic s are defined in figure 2. 2 output signal characteristics are defined in figure 3. 50mv typ optical black pixel 500mv typ reset transient 850mv typ input signal range 05261-002 figure 2. input signal characteristics 2.2v 1v max output signal swing, diffp and diffn 2v p-p max differential signal, diffp?diffn 1.2v diffp gnd diffn 1.7v black level white level 05261-015 figure 3. output si gnal characteristics
ad9940 rev. 0 | page 5 of 20 digital specifications t min to t max , avdd = dvdd = ovdd = tcvdd = hvdd = rgvdd = 2.7 v, ?25c to +85c, unless otherwise noted. table 3. parameter symbol min typ max unit logic inputs high level input voltage v ih 2.1 v low level input voltage v il 0.6 v high level input current i ih 10 a low level input current i il 10 a input capacitance c in 10 pf logic outputs high level output voltage, i oh = 2 ma v oh 2.2 v low level output voltage, i ol = 2 ma v ol 0.5 v cli input high level input voltage v ihCcli 1.85 v low level input voltage v ilCcli 0.85 v rg-driver and h-driver outputs (powered by hvdd, rgvdd) high level output voltage (at max output current) v oh vdd ? 0.5 v low level output voltage (at max output current) v ol 0.5 v maximum output current (programmable) h-driver (per output) 64 ma rg-driver, hl-driver 15 ma maximum load capacitance h-driver (per output) 100 pf rg-driver, hl-driver 50 pf timing specifications (slave timing mode) see figure 10 for timing diagram. table 4. parameter symbol min typ max unit master clock (cli) cli clock period t cli 18 ns cli high pulse width t adc 9 ns internal delay from cli to first tap t clidly 6 ns sample clocks shp rising to shd rising t s1 7.4 9 ns adclk edge placement for ad9941 t rec 3 ns serial interface maximum sck frequency f sclk 10 mhz sl to sck setup time t ls 10 ns sck to sl hold time t lh 10 ns sdata valid to sck rising edge setup t ds 10 ns sck rising edge to sdata valid hold t dh 10 ns
ad9940 rev. 0 | page 6 of 20 absolute maximum ratings table 5. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter rating avdd and tcvdd to avss ?0.3 v to +3.9 v ?0.3 v to +3.9 v hvdd and rgvdd to hvss and rgvss dvdd and ovdd to dvss and ovss ?0.3 v to +3.9 v any vss to any vss ?0.3 v to +0.3 v clpob/hblk to dvss ?0.3 v to dvdd + 0.3 v thermal characteristics sck, sl, and sdi to dvss ?0.3 v to dvdd + 0.3 v rg to rgvss ?0.3 v to rgvdd + 0.3 v ja is measured using a 4-layer pcb with the exposed paddle soldered to the board. h1Ch4 to hvss ?0.3 v to hvdd + 0.3 v reft, refb, and ccdin to avss ?0.3 v to avdd + 0.3 v thermal resistance for 48-lead lqfp package: junction temperature 150c ja = 92c/w lead temperature (10 sec) 350c thermal resistance for 48-lead lfcsp package: ja = 24c/w 1 1 ja is measured using a 4-layer pcb with the exposed paddle soldered to the board. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad9940 rev. 0 | page 7 of 20 pin configuration and fu nction descriptions 05261-003 48 avss 47 avss 46 nc 45 nc 44 nc 43 nc 42 nc 41 nc 40 reft 39 refb 38 avss 37 avdd 35 ccdin 34 avss 33 shp 30 h1 31 avss 32 shd 36 avss 29 h2 28 hvss 27 hvdd 25 h4 26 h3 2 avss 3 avdd 4 diffn 7 ovdd 6 ovss 5 diffp 1 nc 8 tcvdd 9 cli 10 tcvss 12 dvdd 11 dvss nc = no connect 13 dvss 14 sl 15 dvss 16 sdi 17 sck 18 rst 19 hd 20 nc 21 rg 22 hl 23 rgvss 24 rgvdd pin 1 ad9940 top view (not to scale) figure 4. pin configuration table 6. pin function descriptions pin no. menumonic type description 1 1 nc nc no connect. connect to gnd. 2 avss p analog ground. 3 avdd p analog supply. 4 diffn ao cds output, data (negative). 5 diffp ao cds output, data (positive). 6 ovss p analog output buffer ground. 7 ovdd p analog output buffer supply. 8 tcvdd p analog supply for timing core. 9 cli di reference clock input. 10 tcvss p analog ground for timing core. 11 dvss p digital ground. 12 dvdd p digital logic power supply. 13 dvss p digital ground. 14 sl di 3-wire serial load pulse. 15 dvss p digital ground. 16 sdi di 3-wire serial data input. 17 sck di 3-wire serial clock. 18 rst di hardware reset (low active). low = reset state, high = normal operation. 19 hd di horizontal sync pulse. 20 nc nc do no connect. should be left floating. 21 rg do ccd reset gate clock. 22 hl do hl horizontal clock. 23 rgvss p rg driver ground. 24 rgvdd p rg driver power supply. 25 h4 do ccd horizontal clock 4. 26 h3 do ccd horizontal clock 3. 27 hvdd p horizontal clock driver supply. 28 hvss p horizontal clock driver ground. 29 h2 do ccd horizontal clock 2. 30 h1 do ccd horizontal clock 1. 31 avss p analog ground. 32 shd di test clock input for ccd data phase sampling.
ad9940 rev. 0 | page 8 of 20 pin no. menumonic type 1 description 33 shp di test clock input for ccd reset phase sampling. 34 avss p analog ground. 35 ccdin ai ccd signal input. 36 avss p analog ground (ccd signal input reference). 37 avdd p analog supply. 38 avss p analog ground. 39 refb ao voltage reference bottom by-pass. decoupled to analog ground with a 0.1 f capacitor. 40 reft ao voltage reference top by-pass. decouple d to analog ground with a 0.1 f capacitor. 41 to 46 nc nc no connect. connect to gnd. 47, 48 avss p analog ground. 1 type: ai = analog input; ao = analog output; di = digital input; do = digital output; p = power.
ad9940 rev. 0 | page 9 of 20 data bit descriptions table 7. address data bit content default value name description 0 [0] 0 partsel part select: 0 = select ad9940 1 = select ad9941 [1] 0 testmode always set = 0 [2] 0 sw reset reset registers: 1 = reset all registers to the default values [3] 0 mode 0 = slave mode 1 = master mode [4] 0 standby 0 = normal operation 1 = standby operation [6:5] 0 testmode always set = 0 [7] 0 writemode 0 = write to address 1 to address 13 1 = write to address 14 to address 26 1 [6:0] 0 testmode always set = 0 [7] 0 hblkmaskpol hb lk mask polarity: 0 = h1/h3 low, h2/h4 high 1 = h1/h3 high, h2/h4 low 2 [0] 0 hblktog1_0 [8] hblktog1 position for sequence 0 (bit 8) [1] 0 hblktog1_0 [9] hblktog1 position for sequence 0 (bit 9) [2] 0 hblktog1_0 [10] hblktog1 position for sequence 0 (bit 10) [3] 0 hblktog1_0 [11] hblktog1 position for sequence 0 (bit 11) [7:4] 0 testmode always set = 0 3 [0] 0 hblktog1_0 [0] hblktog1 position for sequence 0 (bit 0) [1] 0 hblktog1_0 [1] hblktog1 position for sequence 0 (bit 1) [2] 0 hblktog1_0 [2] hblktog1 position for sequence 0 (bit 2) [3] 0 hblktog1_0 [3] hblktog1 position for sequence 0 (bit 3) [4] 0 hblktog1_0 [4] hblktog1 position for sequence 0 (bit 4) [5] 0 hblktog1_0 [5] hblktog1 position for sequence 0 (bit 5) [6] 1 hblktog1_0 [6] hblktog1 position for sequence 0 (bit 6) [7] 0 hblktog1_0 [7] hblktog1 position for sequence 0 (bit 7) 4 [0] 0 hblktog2_0 [8] hblktog2 position for sequence 0 (bit 8) [1] 0 hblktog2_0 [9] hblktog2 position for sequence 0 (bit 9) [2] 0 hblktog2_0 [10] hblktog2 position for sequence 0 (bit 10) [3] 0 hblktog2_0 [11] hblktog2 position for sequence 0 (bit 11) [7:4] 0 testmode always set = 0 5 [0] 0 hblktog2_0 [0] hblktog2 position for sequence 0 (bit 0) [1] 0 hblktog2_0 [1] hblktog2 position for sequence 0 (bit 1) [2] 0 hblktog2_0 [2] hblktog2 position for sequence 0 (bit 2) [3] 0 hblktog2_0 [3] hblktog2 position for sequence 0 (bit 3) [4] 0 hblktog2_0 [4] hblktog2 position for sequence 0 (bit 4) [5] 0 hblktog2_0 [5] hblktog2 position for sequence 0 (bit 5) [6] 1 hblktog2_0 [6] hblktog2 position for sequence 0 (bit 6) [7] 0 hblktog2_0 [7] hblktog2 position for sequence 0 (bit 7) 6 [0] 0 hblktog1_1 [8] hblktog1 position for sequence 1 (bit 8) [1] 0 hblktog1_1 [9] hblktog1 position for sequence 1 (bit 9) [2] 0 hblktog1_1 [10] hblktog1 position for sequence 1 (bit 10) [3] 0 hblktog1_1 [11] hblktog1 position for sequence 1 (bit 11) [7:4] 0 testmode always set = 0
ad9940 rev. 0 | page 10 of 20 address data bit content default value name description 7 [0] 0 hblktog1_1 [0] hblktog1 position for sequence 1 (bit 0) [1] 0 hblktog1_1 [1] hblktog1 position for sequence 1 (bit 1) [2] 0 hblktog1_1 [2] hblktog1 position for sequence 1 (bit 2) [3] 0 hblktog1_1 [3] hblktog1 position for sequence 1 (bit 3) [4] 0 hblktog1_1 [4] hblktog1 position for sequence 1 (bit 4) [5] 0 hblktog1_1 [5] hblktog1 position for sequence 1 (bit 5) [6] 1 hblktog1_1 [6] hblktog1 position for sequence 1 (bit 6) [7] 0 hblktog1_1 [7] hblktog1 position for sequence 1 (bit 7) 8 [0] 0 hblktog2_1 [8] hblktog2 position for sequence 1 (bit 8) [1] 0 hblktog2_1 [9] hblktog2 position for sequence 1 (bit 9) [2] 0 hblktog2_1 [10] hblktog2 position for sequence 1 (bit 10) [3] 0 hblktog2_1 [11] hblktog2 position for sequence 1 (bit 11) [7:4] 0 testmode always set = 0 9 [0] 0 hblktog2_1 [0] hblktog2 position for sequence 1 (bit 0) [1] 0 hblktog2_1 [1] hblktog2 position for sequence 1 (bit 1) [2] 0 hblktog2_1 [2] hblktog2 position for sequence 1 (bit 2) [3] 0 hblktog2_1 [3] hblktog2 position for sequence 1 (bit 3) [4] 0 hblktog2_1 [4] hblktog2 position for sequence 1 (bit 4) [5] 0 hblktog2_1 [5] hblktog2 position for sequence 1 (bit 5) [6] 1 hblktog2_1 [6] hblktog2 position for sequence 1 (bit 6) [7] 0 hblktog2_1 [7] hblktog2 position for sequence 1 (bit 7) 10 [0] 0 hblktog1_2 [8] hblktog1 position for sequence 2 (bit 8) [1] 0 hblktog1_2 [9] hblktog1 position for sequence 2 (bit 9) [2] 0 hblktog1_2 [10] hblktog1 position for sequence 2 (bit 10) [3] 0 hblktog1_2 [11] hblktog1 position for sequence 2 (bit 11) [7:4] 0 testmode always set = 0 11 [0] 0 hblktog1_2 [0] hblktog1 position for sequence 2 (bit 0) [1] 0 hblktog1_2 [1] hblktog1 position for sequence 2 (bit 1) [2] 0 hblktog1_2 [2] hblktog1 position for sequence 2 (bit 2) [3] 0 hblktog1_2 [3] hblktog1 position for sequence 2 (bit 3) [4] 0 hblktog1_2 [4] hblktog1 position for sequence 2 (bit 4) [5] 0 hblktog1_2 [5] hblktog1 position for sequence 2 (bit 5) [6] 1 hblktog1_2 [6] hblktog1 position for sequence 2 (bit 6) [7] 0 hblktog1_2 [7] hblktog1 position for sequence 2 (bit 7) 12 [0] 0 hblktog2_2 [8] hblktog2 position for sequence 2 (bit 8) [1] 0 hblktog2_2 [9] hblktog2 position for sequence 2 (bit 9) [2] 0 hblktog2_2 [10] hblktog2 position for sequence 2 (bit 10) [3] 0 hblktog2_2 [11] hblktog2 position for sequence 2 (bit 11) [7:4] 0 testmode always set = 0 13 [0] 0 hblktog2_2 [0] hblktog2 position for sequence 2 (bit 0) [1] 0 hblktog2_2 [1] hblktog2 position for sequence 2 (bit 1) [2] 0 hblktog2_2 [2] hblktog2 position for sequence 2 (bit 2) [3] 0 hblktog2_2 [3] hblktog2 position for sequence 2 (bit 3) [4] 0 hblktog2_2 [4] hblktog2 position for sequence 2 (bit 4) [5] 0 hblktog2_2 [5] hblktog2 position for sequence 2 (bit 5) [6] 1 hblktog2_2 [6] hblktog2 position for sequence 2 (bit 6) [7] 0 hblktog2_2 [7] hblktog2 position for sequence 2 (bit 7)
ad9940 rev. 0 | page 11 of 20 address data bit content default value name description 14 [2:0] 3 rgdrv rg drive strength (resolution = 2.2 ma/step): 0 = off 1 = 2.2 ma 2 = 4.4 ma 7 = 15.4 ma [3] 0 rgpol rg polarity: 0 = normal 1 = inverted [6:4] 3 hldrv hl drive strength (resolution = 2.2 ma/step): 0 = off 1 = 2.2 ma 2 = 4.4 ma 7 = 15.4 ma [7] 0 hlpol hl polarity: 0 = normal 1 = inverted 15 [5:0] 0 hlposloc hl rising edge location [7:6] unused 16 [5:0] 24 hlnegloc hl negative edge location [7:6] 0 unused 17 [5:0] 0 rgposloc rg rising edge location [7:6] unused 18 [5:0] 24 rgnegloc rg negative edge location [7:6] unused 19 [3:0] 7 h2/h4drv h2/h4 drive strength (resolution = 4.3 ma/step): 0 = off 1 = 4.3 ma 2 = 8.6 ma 15 =64.5 ma [7:4] 7 h1/h3drv h1/h3 drive strength (resolution = 4.3 ma/step): 0 = off 1 = 4.3 ma 2 = 8.6 ma 15 = 64.5 ma 20 [5:0] 0 h1posloc h1 positive edge location [6] unused [7] 0 h1/h3pol h1/h3 polarity: 0 = normal 1 = inverted (h2/h4 is opposite polarity of h1/h3) 21 [5:0] 32 h1negloc h1 negative edge location [7:6] unused 22 [5:0] 32 shploc shp sampling location [7:6] 0 unused 23 [5:0] 0 shdloc shd sampling location [7:6] unused 24 [7:0] 0 testmode always set = 0 25 [7:0] 0 testmode always set = 0 26 [7:0] 0 testmode always set = 0
ad9940 rev. 0 | page 12 of 20 serial interface timing all the internal registers of the ad9940 are accessed through a 3-wire serial interface. each register consists of an 8-bit data byte starting with the lsb bit. as shown in every write operation must begin with a write to address 0 to specify part select bit and bank location, then followed with any number of consecutive data words. address 0 is always followed by address 01 or address 14 depending on the value specified for writemode (used for bank selection). figure 5 , the data bits are clocked in on the rising edge of sck after sl is asserted low and the entire 8-bit word is latched in on the rising edge of sl after the last msb bit. consecutive serial writes are per- formed starting with address 0 and ending with an address msb bit prior to asserting sl high. a hard reset is recommended after power-up to reset the ad9940 prior to performing a serial interface write. a hard reset is performed by asserting the rst pin low for a mini- mum of 10 s. the serial interface pins sck, sl, and sdi must be in a know state after the rst has been applied. the ad9940 contains two banks of registers, which are programmed independently. bank 1 consists of the registers located at address 0 to address 13, and bank 2 consists of address 14 to address 26. the writemode register located at address 0 is used to select which register bank is written to. sdat a sck sl d0 d2 d3 d7 d0 d3d2 d7 d0 ... ... ... ... addr 01 d2 d3 d7 d0 d3 d2 d7 ... ... ... ... ... notes 1. any number of adjacent registers can be loaded sequentially, beginning with the lowest address 00. 2. when sequentially loading multiple registers, the exact register length (shown above) must be used for each register. 3. all loaded registers are simultaneously updated on the rising edge of sl. addr n addr n+1 addr 00 d1 d1 d1 d1 t ls t dh t ds t lh 05261-004 figure 5. serial interface operation
ad9940 rev. 0 | page 13 of 20 system overview analog front end operation figure 6 shows the typical system block diagram for the ad9940. the ccd output is processed by the ad9940s afe circuitry, which consists of a correlated double sam- pler (cds) and output buffer. the differential output of the ad9940 provides good signal integrity when interfaced with the ad9941. the ad9940 signal-processing chain is shown in figure 7 , consisting of a dc restore circuit, cds, and output buffer. dc restore to reduce the large dc offset of the ccd output signal, a dc restore circuit is used with an external 0.1 f series coupling capacitor. this restores the dc level of the ccd signal to approximately 1.5 v to be compatible with the 3 v analog supply of the ad9940. to operate the ad9940, all ccd and afe timing parameters are programmed into the ad9940 from the system micro- processor through the 3-wire serial interface. from the system master clock, cli, provided by the image processor or external crystal, the ad9940 generates the ccds horizontal and reset gate clocks and all internal afe clocks. correlated double sampler the cds circuit samples each ccd pixel twice to extract the video information and reject low frequency noise. the timing diagram in the h-drivers for h1 to h4, hl and rg, are included in the ad9940, allowing these clocks to be directly connected to the ccd. an h-drive voltage of up to 3.6 v is supported. figure 10 illustrates how the two internally generated cds clocks, shp and shd, are used to sample the reference level and the data level, respectively, of the ccd signal. the placement of the shp and shd sampling edges is determined by the setting of the shploc (address 22) and shdloc (address 23) control registers. placement of these two clock edges is critical to achieve the best perform- ance from the ccd. ccd h1?h4, hl, rg ad9940 05261-005 v out buffer 0.1 f c in ccdin buf out diffn diffp register data timing generator ad9941 adc out register data digital image processing asic serial interface digital outputs figure 6. typical system block diagram diffn ccdin reft refb ad9940 internal v ref h1?h4, hl, rg timing generation 05261-006 buf cds 1v 2v 0.1 f 0.1 f shp 0.1 f shd shp shd precision timing generation serial interface 1.5v + dc restore diffp figure 7. ad9940 signal-processing chain
ad9940 rev. 0 | page 14 of 20 precision timing, high speed timing generation high speed clock programmability the ad9940 generates flexible, high speed timing signals using the precision timing core. this core is the foundation for generating the timing used for both the ccd and the afe: the reset gate rg, horizontal drivers h1 to h4, and the shp/shd sample clocks. a unique architecture makes it routine for the system designer to optimize image quality by providing precise control over the horizontal ccd readout and the afe corre- lated double sampling. figure 9 shows how the high speed clocks, rg, hl, h1Ch4, shp, and shd are generated. the rg pulse has programmable rising and falling edges, and can be inverted using the polarity control. the horizontal clocks h1/h3 ha ve programmable rising and falling edges, and polarity control. the h2/h4 clocks are always inverses of the h1/h3 h-driver outputs. table 8 summarizes the high speed timing registers and their parameters. each edge location setting is 6 bits wide, but only 48 valid edge locations are available. therefore, the register values are mapped into four qu adrants, with each quadrant containing 12 edge locations. timing resolution the precision timing core uses a 1 master clock input (cli) as a reference. this clock should be the same as the ccd pixel clock frequency. figure 8 illustrates how the internal timing core divides the master clock period into 48 steps or edge positions. therefore, the edge resolution of the precision timing core is (t cli /48). table 9 shows the correct reg- ister values for the corresponding edge locations. notes 1. pixel clock period is divided into 48 positions, providing fine edge resolution for high speed clocks. 2. there is a fixed delay from the cli input to the internal pixel period positions ( p[0] p[48] = p[0] p[12] p[24] p[36] 1 pixel period ... ... cli t clidly position 05261-007 t clidly = 6 ns typ). figure 8. high speed clock resolution from cli master clock input
ad9940 rev. 0 | page 15 of 20 h2/h4 hl ccd signa l rg 1 4 5 6 8 programmable clock positions: 1 rg polarity. 2 rg rising edge. 3 rg falling edge. 4 shp sample location. 5 shd sample location. 6 h1/h3 polarity. 7 h1/h3 rising edge position. 8 h1/h3 falling edge position (h2/h4 are inverse of h1/h3). 9 hl polarity. 10 hl rising edge. 11 hl falling edge. 05261-008 23 h1/h3 7 9 11 10 figure 9. high speed clock programmable locations n n+1 n+2 n+9 n+10 t rec shploc shdloc adclk (for ad9941) diffp diffn ccd signal t s1 05261-009 valid figure 10. shp, shd, and data output timing
ad9940 rev. 0 | page 16 of 20 the rg and hl output drive strength registers are divided into seven 3-bit values, each adjustable in 2.2 ma increments. the minimum setting of 0 is equal to off or three-state, and the maximum setting of 7 is 15.4 ma. h-driver and rg outputs in addition to the programmable timing positions, the ad9940 features on-chip output drivers for the rg and h1 to h4 out- puts. these drivers are powerful enough to directly drive the ccd inputs. the h-driver and rg driver current can be adjusted for optimum rise/fall time into a particular load using the h1/h3drv, h2/h4drv, rgdrv, and hldrv registers the horizontal output drive strength register is divided into fifteen different 4-bit values, each one adjustable in 4.3 ma increments. the minimum setting of 0 is off or three-state, and the maximum setting of 15 is 64.5 ma. figure 11 as shown in , the h2/h4 outputs are inverses of h1/h3. the internal propagation delay resulting from the signal inversion is less than l ns, which is significantly less than the typical rise time driving the ccd load. this results in an h1/h2 crossover voltage at approximately 50% of the output swing. the crossover voltage is not programmable. table 8. timing core register paramete rs for h1, h3, rg1, rg2, and shp/shd parameter length (bits) range description polarity 1 high/low polarity control for h1/h3, rg1, and rg2: 0 = no inversion. 1 = inversion. positive edge 6 0 to 47 edge location positive edge location for h1/h3, rg1, and rg2. negative edge 6 0 to 47 edge location negati ve edge location for h1/h3, rg1, and rg2. sample location 6 0 to 47 sample location sampling location for shp and shd. h-drive control 4 0 to 15 current steps drive current for h1 to h4, 0 to 15 steps of 4.3 ma each. rg-drive control 3 0 to 7 current steps drive current for rg, 0 to 7 steps of 2.2 ma each. hl-drive control 3 0 to 7 current steps drive current for hl, 0 to 7 steps of 2.2 ma each. fixed crossover voltage h1/h3 h2/h4 t pd h2/h4 h1/h3 t rise t pd << t rise 05261-010 figure 11. h-clock inverse phase relationship table 9. precision timing edge locations quadrant edge location (decimal) register value (decimal) register value (binary) i 0 to 11 0 to 11 00 0000 to 00 1011 ii 12 to 23 16 to 27 01 0000 to 01 1011 iii 24 to 35 32 to 43 10 0000 to 10 1011 iv 36 to 47 48 to 59 11 0000 to 11 1011
ad9940 rev. 0 | page 17 of 20 individual hblk sequences hblk sequences up to three individual hblk sequences are available in each line. this allows special h-blanking as shown in the hblk programmable timing shown in figure 12 is programmed using the hblktog registers. only the toggle positions are used to designate the start and the stop posi- tions of the blanking period. additionally, a polarity control, hblkmaskpol, designates the polarity of the horizontal clock signals h1 to h4 during the blanking period. setting hblkmaskpol high sets h1 = h3 = high and h2 = h4 = low during the blanking. figure 14 . the hblk sequences are sequential starting with sequence 0. to ensure proper hblk operation, the following sequence is required for values programmed in the hblktog registers: hblktog1_0 < hblktog2_0 < hblktog1_1 < hblktog2_1 < hblktog1_2 < hblktog2_2 cli 05261-011 0123456789 pixel cloc k 0123456789 t clidly 13 2 hd h1/h3 h2/h4 programmable settings: 1 hblktog1_n (n = 0, 1, 2) 2 hblkmaskpol 3 hblktog2_n (n = 0, 1, 2) figure 12. horizontal blanking example showing hblktog1_0 = 0, hblkmaskpol = 0, and hblktog2_0 = 3 hd hblk note 1. the polarity of h1 during the blanking region is programmable (h2 has the opposite polarity of h1). h1/h3 h1/h3 h2/h4 ... ... 05261-012 figure 13. hblk masking control
ad9940 rev. 0 | page 18 of 20 hblk special h-blank pattern is created using multiple hblk toggle positions. h1/h3 h2/h4 05261-013 hd 12 34 5 6 programmable settings: 1 hblktog1_0 2 hblktog2_0 3 hblktog1_1 4 hblktog2_1 5 hblktog1_2 6 hblktog2_2 figure 14. generating special hblk patterns
ad9940 rev. 0 | page 19 of 20 applications information all signals should be carefully routed on the pcb to main- tain low noise performance. the ccd output signal should be connected to the ccdin pin through a 0.1 f capacitor. the ccd timing signals h1a/b to h2a/b and rg1 to rg2 should be routed directly to the ccd with minimum trace lengths. the clock inputs are located on the other side of the package, where the analog pins are located, and should be connected to the digital asic away from the analog and ccd clock signals. all decoupling capacitors should be located as close as possible to the package pins. careful use of a split ground plane can be effective to avoid the return current of horizontal driver flows into analog ground, thereby reducing coupling noise. power-supply decoupling is very important for achieving low noise performance. figure 15 shows the local high frequency decoupling capacitors, but addi tional capacitance is recom- mended for lower frequencies. additional capacitors and ferrite beads can further reduce noise. a single ground plane is recommended for the ad9940. this ground plane should be as continuous as possible, particularly where analog pins are concentrated, to ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. when using the lfcsp package, it is recommended that the exposed paddle on the bottom of the package be soldered to a large pad, with multiple vias connecting the pad to the ground plane. 05261-014 48 avss 47 avss 46 nc 45 nc 44 nc 43 nc 42 nc 41 nc 40 reft 39 refb 38 avss 37 avdd 35 ccdin 34 avss 33 shp 30 h1 31 avss 32 shd 36 avss 29 h2 28 hvss 27 hvdd 25 h4 26 h3 2 avss 3 avdd 4 diffn 7 ovdd 6 ovss 5 diffp 1 nc 8 tcvdd 9 cli 10 tcvss 12 dvdd 11 dvss 13 dvss 14 sl 15 dvss 16 sdi 17 sck 18 rst 19 hd 20 nc 21 rg 22 hl 23 rgvss rgvdd 24 pin 1 ad9940 top view (not to scale) 0.1 f 0.1 f 0.1 f 3v analog suppy 0.1 f 0.1 f diffn output diffp output 3v analog supply 3v analog supply 3v analog suppl y 3v analog supply master clock input 4.7 f 0.1 f + 0.1 f 3 serial interface rst input hd input rg hl 0.1 f 3v analog supply horizontal clocks to ccd 4.7 f 0.1 f + 2 ccd sampling inputs analog output from ccd 3v analog supply 4 figure 15. recommended circuit configurat ion nc pin and supply name consistency
ad9940 rev. 0 | page 20 of 20 outline dimensions compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 7.00 bsc sq 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 figure 16. 48-lead low profile quad flat package [lqfp} (st-48) dimensions shown in millimeters pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 figure 17. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm x 7mm body, very thin quad (cp-48-1) dimensions shown in millimeters ordering guide model temperature range package description package option AD9940BSTZ 48-lead low profile quad flat package [lqfp] st-48 ? 25c to +85c 1 AD9940BSTZrl 48-lead low profile quad flat package [lqfp] 1 ? 25c to +85c st-48 ad9940bcpz 48-lead lead frame chip scale package [lfcsp_vq] 1 ? 25c to +85c cp-48-1 ad9940bcpzrl 48-lead lead frame chip scale package [lfcsp_vq] cp-48-1 ? 25c to +85c 1 1 z = pb-free part. ?2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05261C0C7/05(0)

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